The present invention relates to a memory cell having a variable resistance element.
An NOR or an NAND flash memory has been typically used as a semiconductor nonvolatile memory for data storage. However, such a flash memory needs a high voltage for writing and erasing, and besides, is limited in number of electrons to be injected into a floating gate. Consequently, limitation in size reduction of the flash memory is pointed out.
At present, a resistance change memory such as PRAM (Phase Change Random Access Memory) or PMC (Programmable Metallization Cell) is proposed as a next-generation nonvolatile memory that may exceed a limit in size reduction of the nonvolatile memory (patent documents 1 and 2, and non-patent documents 1 to 3). Each of the memories described in the patent document 2 and the non-patent documents 1 to 3 has a simple structure where a resistance change layer is sandwiched between electrodes, and a memory described in the patent document 1 has a structure where an ion source layer and a resistance change layer are sandwiched between electrodes. In PMC or PRAM, it is considered that an atom or an ion is moved by heat or an electric field, so that a conduction path is formed, and consequently resistance change is exhibited.    Patent document 1: Japanese Unexamined Patent Application Publication No. 2006-196537    Patent document 2: Japanese Unexamined Patent Application Publication No. 2006-322188    Non-patent document 1: Szot, et al., Nature Material, 1614, p. 312 (2006)    Non-patent document 2: Sakamoto, et al., Solid Electrolyte Memory, OYO BUTURI, 75, p. 1126, September 2006    Non-patent document 3: Sawa, Resistance-Change Nonvolatile Memory Using Transition-Metal Oxide, OYO BUTURI, 75, p. 1109, September 2006